1. Field of the invention
The present invention relates to an improvement on LFSR (linear feedback shift register) used for BIST (built-in self-test).
2. Related Prior Art
BIST (built-in self-test) is typical of the “design for testability” techniques applicable especially to SoC (system-on-chip). It is considered the most appropriate choice for testing SoC. The most important advantage of BIST is that it does not use external testers, but uses test functions built into the individual chip, thus the test costs are reduced and testing is possible even during the manufacturing process or when in use. For performing BIST, entering test patterns is required. LFSR is commonly used to generate a pseudo-random pattern that is one type of test pattern.
Conventionally, referring to FIG. 1, an over-transition problem appears at scan chain 13, because of the low degree of association between the patterns generated in LFSR 10. To solve this problem, as shown in FIG. 1, the conventional circuit additionally includes a k-input AND gate 11 and a toggle flip-flop (T-FF) 12. FIG. 1 also shows block-wise a conventional structure of LT-RTPG (low transition random test pattern generator).
In FIG. 1, the number of inputs, “k,” is determined by toggle probability. Empirical studies say the optimum value of k is 2 or 3. The LFSR 10 is connected to such inputs of the AND gate 11, and the T-FF 12 is operated according to the outputs of the AND gate 11, thereby patterns having high association are provided.
The T-FF 12 outputs “1” only if toggle occurs in the input values (i.e., when successive input vectors have different values; this is referred to as “transition”), while it outputs “0” otherwise. Therefore, in connection with the AND gate, by entering patterns having high association in the scan chain 13, a low power LFSR can be implemented. That is, in a k-input AND gate, the probability of generating “1” is 1/2 k, and the transition occurs at the T-FF before and after this “1” generation. The scan chain shifts until the scan chain is filled with these test patterns. At this time, by applying test patterns having high association to the scan chain, the number of transitions can be reduced.
There was a test performed using the above conventional art, which used an ISCAS '89 benchmark circuit. The test result discloses that the scan transitions were reduced by about 30%. However, the test was performed only on circuits smaller than an s9234 circuit, and test results on a large scale circuit which had hundreds or thousands of scans could not be found. The reason for the absence of such test results is presumed to be that more patterns were required to find faults when varying the random patterns on the circuit shown in FIG. 1. Actually, in the above test result, it was noted that 131,072 test patterns were used to obtain 91.78% of the fault coverage.
In the conventional technique, although it comprises a k-input AND gate as well as a T flip-flop, its hardware overhead cannot be said to be very large. However, the inventors have studied a method to further reduce the scan transition numbers and to improve the fault coverage, thereby developing a new concept for a transition monitoring window and a novel low power LFSR structure by using the same.